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4:1 Multiplexer Dataflow Model in VHDL with truth table.

VHDL code for multiplexer using dataflow method – full code and explanation.


A multiplexer is a combinational logic circuit that has several inputs, and only one output and select lines. The input line is chosen by the value of the select inputs. A general multiplexer is with n inputs, m select lines, and one output line is shown below.






Truth table of a 4:1 Mux



VHDL code for multiplexer using the dataflow method.


use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX4_1 is
  Port( i :in STD_LOGIC_VECTOR(3 downto 0);
        s :in STD_LOGIC_VECTOR(1 downto 0);
        y :out STD_LOGIC);
end MUX4_1;
architecture dataflow of MUX4_1 is
begin
with s select
y <=     i(0) when "00",
         i(1) when "01",
         i(2) when "10",
         i(3) when others;
end dataflow;




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